1. Field of the Invention
The present invention relates to a dynamic random access memory (RAM), and in particular to improved sense amplifier circuitry for sensing data stored in the memory.
2. Description of the Prior Art
A dynamic RAM in which memory cells are integrated into high packing density for a large memory capacity is an important feature to improve the control and operational functions of electronic appliances and to reduce the size thereof. However, in order to manufacture a dynamic RAM ("DRAM") of this type to the desired characteristics, various kinds of technology are required to be developed. This also applies to the technology required to increase the operation speed of the sense amplifier. Consequently, various types of DRAMs associated with sense amplifiers configured according to new designs and ideas has been proposed.
As well known, a MOS DRAM, for example, includes a memory cell array in the form of columns such that each array has memory cells arranged between a pair of bit lines and a plurality of word lines intersecting the bit lines, with each memory cell connected between one of the word lines and one of the bit lines.
In order to implement a high-speed access and a low power consumption for a DRAM of this construction there has been a tendency to employ complementary MOS (CMOS) technology. In association therewith, the sense amplifier circuitry is also formed in the CMOS structure. For example, in "the Analysis of CMOS Sense Amplifier" written by M. Yoshida in the National Convention Record, 1985 of the Institute of Electronics and Communication Engineers of Japan, No. 528 (Mar. 27-30, 1985), the author described an analysis on operations of a CMOS sense amplifier according to a bit-line half-precharge method. In this method, two bit lines constituting a bit line pair are connected to each other to form a short circuit there-between, so as to attain an average of a high-level voltage and a low-level voltage of the previous operating cycle, thereby setting the average as a precharge potential level for the bit lines. This precharge potential level is substantially intermediate or approximately halfway between (thus, a "half-precharge" method) a power source potential (Vcc, for example) and a ground potential.
This type of sense amplifier circuit has two sense amplifiers connected between a pair of bit lines such that one of the sense amplifiers is a sense amplifier including an n-type channel comprising a pair of MOS transistors having n-type channels in which control gates are crosswise connected. The other sense amplifier is a sense amplifier including a p-type channel comprising a pair of MOS transistors having p-type channels in which control gates are also crosswise connected. In a read operation of the memory cell, these sense amplifiers are supplied with complementary read clocks in complementary phases to each other. The paired bit lines are linked via a switching circuit including a pair of transistors to a pair of data buses. The switching circuit undergoes a switching operation under the control of a column decoder.
However, in a case where the DRAM structure above is applied to a memory of a large capacity, a problem arises that at a time when the sense amplifier is enabled, due to a large capacitance of the bit line, a long period of time is required for the sense amplifier to conduct charge/discharge operations on the bit line for the sense operation. Furthermore, in a case of a configuration in which the electrostatic capacity of the data bus is greater than that of the paired bit lines selected by the column decoder, there occurs an additional problem that, in an operation to select a column line, the potential difference between the paired bit lines is decreased, which elongates the period of time to transmit data to the data bus. Consequently, it is a problem to implement a DRAM to be driven for a high-speed access.